CIF 3

Implementation phase

Once you have validated your supervisor during the simulation phase, you can proceed with the implementation phase, to test the supervisor on the actual hardware.

For the four workstations of the 4K420 course files, PLC code is generated. The PLC code is used in conjunction with TwinCAT, to control the hardware setups via a soft PLC.

If you developed a controller for a different system, and you want to control that machine through PLC code as well, most of the information for this phase will be relevant, especially if you also use TwinCAT. If you use a different approach to control the system, or to a lesser extent if you do use PLC code but not TwinCAT, you’ll have to do more work by yourself.

During this phase, you should validate that the supervisor correctly controls the hardware, i.e. that is does not allow for any undesired behavior, while it still allows for all the desired behavior. If not, go all the way back to your initial plants and requirements. If the hardware functions correctly with your supervisor, you’ve reached your goal.

Testing the correct behavior of your supervisor directly on the hardware, instead of first via simulation, may feel like a fast way to solve your control problem, but remember:

  • You need to have access to the hardware.
  • Each experiment needs you to reset the physical machine.
  • You cannot check all possible traces.
  • You may be tempted to ‘do without thinking’, especially when the system is ‘almost working’.
  • If your supervisor doesn’t work, you may damage the physical system.

Implementation for the 4K420 workstations

The 4K420 course files provide for each of the workstations a #_hw.cif file (where # is to be replaced by the name of your system, as usual). This file, generally called the hardware mapping file, serves several purposes. First, it couples the events of the supervisor to the actual sensor and actuator ports of the hardware. Secondly, it provides software implementations of the timers, which are not available as physical hardware. These timers are identical to the timers of the hybrid simulation model. Finally, it takes care of the initialization of the system, to ensure that the system is in the state that the supervisor assumes is the initial state, as we modeled it in the plant automata.

To generate the PLC code, first you’ll need to merge the (merged) supervisor from the supervisor synthesis phase, the disabled events file generated during the event disabler phase, and the hardware mapping file together into a single file. Then, you can use the PLC code generator to generate the PLC code in a format that TwinCAT can understand.

Similar to the previous phases, a script is provided to automate these tools. The 3_gen_plc_code.tooldef2 script automatically performs all the necessary steps (synthesize, merge, disable, etc) to generate the file that can be used by the PLC code generator. To execute the script, right click it and choose Execute ToolDef. The script is smart enough to prevent regeneration of files that are already up-to-date. Once the file is available, the script starts the PLC code generator, using the appropriate settings.

Before executing the script however, make sure you’ve turned on the power supplies (three in total for all four workstations), and the compressed air valve (one valve for all stations) is opened (handle in the vertical position). Also make sure to turn on the computer next to the workstation, if it is not already on. Then, you need to follow some steps on the computer next to the workstation, taking into account the following:

  • When asked to provide a name for the TwinCAT project and solution, choose #_plc (where # is replaced by the name of your workstation). Create the solution in the directory that contains the CIF file with your plants and requirements, on your G drive (network share).
  • When instructed to run the script, execute the 3_gen_plc_code.tooldef2 script.
  • When instructed to load TwinCAT I/O mappings, use the #_twincat_io_mapping.xml file provided by the 4K420 course files.

The steps further describe all you need to be able to do in TwinCAT, to control the physical hardware setup, and can be found in the TwinCAT usage section of the TwinCAT PLC output page. That page also provides further information on the use of TwinCAT. In particular, if you run into problems using TwinCAT, read the Frequently Asked Questions (FAQ) section of that page.

If your supervisor is too large, TwinCAT may not be able to handle it. In that case, read the Using multiple plants/requirements files section. By splitting your system into parts and synthesizing a supervisor per part, you get more but smaller supervisors. This significantly reduces the size of the generated PLC code, and solves many implementation issues.

Discrepancies between simulation and implementation

Your supervisors may work correctly during simulation, but behave differently and incorrectly in the implementation. This can have several causes.

The most common cause is that the simulator may choose different traces than the implementation. In such cases, you should use the simulator to try different traces as well. For more information, see the Simulation and traces section.